Adrián Rios
Hardware Design Engineer | Barcelona, Spain
A highly motivated and skilled computer engineer with hands-on experience in RTL coding, AI accelerators, RISC-V CPUs architectural design, and hardware verification. Proficient in SystemVerilog, VHDL, and UVM, with a strong understanding of RISC-V architecture.
Experience
Hardware Design Engineer
Barcelona Supercomputing Center | Jun 2024 – Present
- Designing and implementing RTL for Out-of-Order Core development.
- Implemented and verified a Fetch Directed Instruction Prefetcher for bachelor’s thesis (9.2/10).
Intern – BSC International Internship Programme
Barcelona Supercomputing Center | Feb 2024 – Jun 2024
- Performed UVM code coverage and implemented additional UVM features.
Intern – BSC International Summer HPC Internship Programme
Barcelona Supercomputing Center | Jul 2023 – Sep 2023
- Performed functional coverage verification for the RISC-V Vector Extension v1.0.0.
Education
Master in Innovation and Research in Informatics
Universitat Politècnica de Catalunya (UPC), Barcelona | Sep 2024 – Dec 2026
- Specialty in High Performance Computing, focused on Digital Design.
Computer Engineering Degree
Universitat Politècnica de Catalunya (UPC), Barcelona | 2020 – 2024
- 3 Highest Honors: Digital Signal Processing, Design of Microcomputer-Based Systems, Data Processing Centers.
- Excellence in: Architecture-aware Programming, Parallel Programming and Architectures.
Skills
SystemVerilog
VHDL
UVM
RISC-V
X86
Digital Design
C
C++
Python
Bash
Git
Linux
Creativity
Proactivity
Team Spirit
Leadership
Languages
English (C1)
Spanish (Native)
Catalan (Native)
Interests
Scuba Diving
Hiking