Adrián Rios
Hardware Design Engineer | Barcelona, Spain | Willing to relocate
Hardware Design Engineer at Barcelona Supercomputing Center (BSC) with strong experience in RTL design, out-of-order processor development, and hardware verification for high-performance computing and AI accelerators. Passionate about designing high-performance, energy-efficient microarchitectures for CPUs and domain-specific accelerators.
Experience
Hardware Design Engineer
Barcelona Supercomputing Center | Jun 2024 – Present
- Designed and implemented RTL for out-of-order superscalar RISC-V core development, including branch predictors and prefetchers, as well as their respective testbenches using the Python cocotb framework for unit testing.
- Conducted performance evaluation through benchmarks and microbenchmarks of the entire CPU architecture, performing advanced statistical analysis to identify bottlenecks and propose solutions.
- Implemented and verified a Fetch-Directed Instruction Prefetcher for my bachelor’s thesis (9.2/10)
Intern – BSC International Internship Programme
Barcelona Supercomputing Center | Feb 2024 – Jun 2024
- Implemented additional UVM features for an out-of-order superscalar RISC-V core, including CSRs verification and a custom RISC-V instruction extension using Spike (DPI-C) as reference model.
- Implemented UVM features for an in-order RISC-V core and integrated functional ISA coverage for the RVV 1.0.0 vector extension.
- Improved code and functional coverage, bumping up results more than 30% through targeted tests, deadcode removal, and smart regression methodologies.
Intern – BSC International Summer HPC Internship Programme
Barcelona Supercomputing Center | Jul 2023 – Sep 2023
- Implemented and analyzed functional coverage verification for a Vector Processing Unit (VPU) using the RISC-V Vector Extension v1.0.0.
- Implemented and analyzed functional coverage verification for the VPU communication protocol and interface with the core.
- Implemented and analyzed functional (ISA and interface) coverage verification for an out-of-order superscalar core Floating Point Unit.
Projects
RAIG: Radiation-Hardened AI Gateway
Main architect (Academic Project 10/10 with highest honors) • RAIG documentation • raig.pages.dev
- Designed and implemented a radiation-hardened multi-TPU architecture (RAIG) in SystemVerilog, including systolic arrays, custom ISA extensions, and memory-coherent multi-core integration for AI inference workloads.
- Led end-to-end hardware development (architecture, RTL, and verification) of tensor accelerators, optimizing matrix multiplication (GeMM), dataflow, and instruction scheduling.
- Developed a configurable AI accelerator framework supporting parallel and lockstep execution for fault-tolerant operation in safety-critical environments.
Meta-Perceptron Branch Predictor
Architect (Academic Project 9.5/10) • Meta-Perceptron documentation and src code
- Implemented a Meta-Perceptron dynamic branch predictor in C++ for Champsim simulator, combining Gshare and Bimodal predictors using a perceptron selector.
- Achieved better accuracy than the classical metapredictor while maintaining lower storage cost and improved scaling.
- Introduced target history to reduce aliasing and proved better memory scalability, allowing chaining of multiple metapredictors.
Education
Master in Innovation and Research in Informatics
Universitat Politècnica de Catalunya (UPC), Barcelona | Sep 2024 – Dec 2026
- Specialty in High Performance Computing, focused on Digital Design.
- 2 Highest Honors (10/10): Processor Design, Multiprocessor Architecture
- Excellence in: Advanced Processor Architecture (9.5/10), Supercomputer Architecture (9.99/10), Supercomputing for Challenging Applications (9.4/10).
Computer Engineering Degree
Universitat Politècnica de Catalunya (UPC), Barcelona | 2020 – 2024
- 3 Highest Honors: Digital Signal Processing, Design of Microcomputer-Based Systems, Data Processing Centers.
- Excellence in: Architecture-aware Programming, Parallel Programming and Architectures.